
module spi_rx(
    input                               clk_i,
    input                               rstn_i,

    input                               rx_en_i,
    input                               spi_CLK_pos_r_i,
    input                               spi_rx_i,

    output reg [7:0]                    spi_rx1B_o,
    output reg                          spi_rx1B_done_o
);

reg [3:0]                               bit_cnt;
wire                                    bit_cnt_flag;

assign bit_cnt_flag = (bit_cnt == 'd7) ? 1'b1 : 1'b0;
always@(posedge clk_i or negedge rstn_i)begin
    if(!rstn_i)begin
        bit_cnt <= 'd0;
    end
    else if(!rx_en_i)begin
        bit_cnt <= 'd0;
    end
    else if(bit_cnt_flag && spi_CLK_pos_r_i)begin
        bit_cnt <= 'd0;
    end
    else if(spi_CLK_pos_r_i)begin
        bit_cnt <= bit_cnt + 1'b1;
    end
    else begin
        bit_cnt <= bit_cnt;
    end
end

always@(posedge clk_i or negedge rstn_i)begin
    if(!rstn_i)begin
        spi_rx1B_done_o <= 'd0;
    end
    else if(bit_cnt_flag && spi_CLK_pos_r_i)begin
        spi_rx1B_done_o <= 'd1;
    end
    else begin
        spi_rx1B_done_o <= 'd0;
    end
end

always@(posedge clk_i or negedge rstn_i)begin
    if(!rstn_i)begin
        spi_rx1B_o <= 'd0;
    end
    else if(!rx_en_i)begin
        spi_rx1B_o <= 'd0;
    end
    else if(spi_CLK_pos_r_i)begin
        spi_rx1B_o <= {spi_rx1B_o[6:0], spi_rx_i};
    end
end
endmodule